1. Field of the Invention
The present invention relates to a logic circuit suitable for use in a semiconductor integrated circuit, and particularly to a logic circuit composed of CMOS (Complementary Metal Oxide Semiconductor) circuitry, which consumes less power when the power is turned on or the circuit is not in use, and enables the power switch to be quickly turned on and off.
2. Description of the Related Art
With the growing demand for fine-fabrication and low power consumption, the power supply voltage for semiconductor integrated circuits has been decreasing year by year. In particular, the spread of portable battery-powered equipment such as mobile phones has been accelerating the demand for low power consumption. In semiconductor integrated circuits, particularly CMOS circuits, power is mostly consumed as switching power. The switching power is in proportion to the square of the power supply voltage and decreasing the power supply voltage is therefore the most effective means for reducing power consumption.
However, if the power supply voltage is decreased, the transistor drive capability will considerably decline and the operating speed will go down as the power supply voltage becomes close to the transistor's threshold voltage. To avoid this, it is necessary to lower the threshold voltage. As the threshold voltage is lowered, leakage current, which should be incommensurably smaller than the switching power, would increase exponentially and come to consume non-negligible power. It is expected that as the tendency towards further fine fabrication and lower power supply voltages continues, more power will be consumed for current leakage than for switching. Whereas the switching power is consumed only during operation of the circuit, power consumption due to leakage current continues while the power is on. When the circuit is not used for a long period, leakage current would become a dominant power consumer. Therefore it has been a common practice to turn off the whole circuitry or unnecessary circuits in order to reduce power consumption.
Another problem is that when the circuit is switched on after it has not been used for a long time, the voltage levels of output nodes of transistors may be inverted almost at the same time and at that time there occurs a flow of short-circuit current. This short-circuit current becomes one of the major reasons for increase in power consumption.
For example, JP-A No.29834/1994 (Literature 1) discloses a logic circuit in which a power switch (hereinafter called a “power switch MOS”) composed of a high-threshold MOS transistor, which is disposed between a logic circuit composed of low-threshold MOS transistors and a power line pair, is turned off while the circuit is inactive to prevent leakage current to the power line pair. The power switch MOSs may be disposed between the logic circuit and both the power lines. Further, in case of that the logic circuit includes a plurality of circuit stages, the power switch MOS may be disposed alternately between each circuit stage and one of the power line pair, according to the state of each circuit stage in the standby state.
JP-A No. 291929/1993 (Literature 2) discloses a logic circuit that adopts the circuit configuration as previously described regarding Literature 1 and adds a level hold circuit to an output node of the logic circuit in order to hold a level of the output node when the power switch MOS is turned off. The level hold circuit, which is composed of a high-threshold MOS transistor, is directly connected to the power line pair. Here, in an inverter chain where plural inverters are connected in cascade, the power supply is divided into odd-numbered inverters and even-numbered inverters. That is, the power supply voltage is supplied through different high-threshold power switch MOSs respectively to odd-number inverters and even-numbers inverters. Furthermore, two level hold circuits composed of high-threshold transistors are added respectively to the output node of the last odd-number inverter and the output node of the last even-number inverter. The level hold circuits are directly connected to the power line pair; in the inverter chain, when the power switch MOSs are turned off while the inverter chain is inactive, the level hold circuits hold the output levels. In the logic circuit as described in Literature 1, all nodes of the logic circuit reach the same level as the output node when the power switch MOS remains off for a long time. On the other hand, in the inverter chain as described in Literature 2, the nodes alternately reach the same level as the output node of the last odd-number inverter or the output node of the last even-number inverter and each inverter may hold the output level before a switching-off operation. Only when that is the case, no short-circuit current flows when the switch is turned on, even after a long switch-off period.
JP-A No. 86916/1995 (Literature 3) discloses a circuit which has not only a power switch MOS but also a NAND gate before the logic circuit input node. The NAND gate is used to fix the preceding circuit's output node to a level in which short-circuit current does not flow upon a switching-on operation after a long switch-off period. In this circuit configuration., it is possible to prevent short-circuit current from flowing upon a switching-on operation not in a particular case but in any case.
Literature 3 reveals a technique which reduces both leakage current and short-circuit current when the power supply voltage is low. However, this technique is intended to be applied to a simple single-input logic circuit. In a logic circuit for multiple inputs, the node levels change from high to low or vice versa depending on input and thus it is impossible to uniquely decide to which line of the power line pair to connect the power switch MOS. If that is the case, the power supply voltage must be gradually changed in order to prevent an increase in short-circuit current. Therefore, it would be impossible to turn on and off the power as frequently as necessary or quickly.
The primary object of the present invention is to provide a logic circuit which assures short-circuit current reduction by using a gate which uniquely fixes the level of each node and also reduces leakage current so that the power is turned on and off quickly.